1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor devices, and more particularly, to methods for forming dual damascene structures with tapered via portions and improved performance.
2. Brief Discussion of the Related Art
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require increasingly sophisticated interconnection technology. As device sizes decrease it has been increasingly difficult to provide interconnection technology that satisfies the requirements of low resistance and capacitance interconnect properties, particularly where submicron interlayer and intralayer interconnects have increasingly high aspect ratios. In particular, high aspect ratio vias require uniform etching profiles including preventing formation of unetched residues around the via openings during anisotropic etching of an overlying trench structure in a dual damascene formation process.
In a typical dual damascene process, via openings are first etched into an insulating layer also known as an inter-metal or inter-level dielectric (IMD/ILD) layer. The insulating layer is typically formed over a metal or conductive layer. After a series of photolithographic steps defining via openings and trench openings, the via openings and the trench openings are filled with a metal (e.g. Cu) to form vias and trench lines, respectively. The excess metal above the trench level is then removed and the uppermost layer planarized usually by a chemical-mechanical polishing (CMP) process.
One shortcoming of the above approach during the formation of the via and trench openings is punchthrough. Typically in dual damascene processing, etching stop layers and via plugs are formed in the dual damascene structure to prevent punchthrough that may occur during the anisotropic etching of the insulating layer to form the via and trench openings. If etching of the insulating layer continues into the metal layer, the metal will be exposed and there may be metal oxidation leading to device failure. With many variables involved, it has proven difficult to achieve consistent etching results. For this reason, in the conventional dual damascene methods, high thickness and/or low etch rate via plugs are typically formed in the via openings to prevent the punchthrough phenomenon.
Another drawback and a recurring problem affecting the anisotropic etching of sub-micron dual damascene features, particularly with respect to the trench portion etching process has been the formation of photoresist residues (also referred to as scum) leading to via fences. These residues frequently remain on via sidewalls detrimentally affecting subsequent etching profiles. For example, during anisotropic etching of a trench opening overlying one or more vias, residual photoresist interacting with the IMD layer at the via sidewall produces an etching resistant residue surrounding the via opening following trench etching. The via fence detrimentally affects subsequent processes, for example, by reducing adhesion of deposited overlayers, for example barrier layers and metal filling layers which degrades electrical performance and device reliability.
For example, referring to FIG. 1 is shown a dual damascene structure following trench etching which shows metal layer 8, etching stop layer 10, IMD layer 12A, IMD layer 12B, and photoresist layer 14. For example, via opening 16A is first formed by a first conventional photolithographic patterning and etching process followed by formation of an overlying trench opening 16B by a similar second photolithographic patterning and etching process. Following trench etching, an etching resistant via fence 22 is formed surrounding the via opening 16A.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need in the semiconductor processing art to develop a method or methods to reliably etch dual damascene structures to at least avoid via fences and have improved electrical performance.